1. Field of the Invention
The invention relates to the process of fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus to reduce the amount of resolution enhancement applied to a die by selectively modifying transistor gate lengths to improve the speed of critical transistors that affect timing of a circuit, while limiting the static power consumption of other transistors in the circuit
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. Reducing the feature size increases the speed at which circuits can operate and increases the number of circuit elements that can be incorporated onto a semiconductor chip.
Unfortunately, as feature size continues to decrease, off-state leakage current from transistors increases, which can greatly increase the static power consumption of a chip. Hence, circuits with tens of millions of transistors fabricated with 130 nm and below process technology have to tradeoff performance with off-state leakage current.
High performance is achieved through faster transistors that have small gate-lengths and low threshold voltages. However, these fast transistors also have large off-state leakage currents. Referring to FIG. 1, a polysilicon field effect transistor 100 is comprised of a polysilicon line 104 that forms a transistor gate 106 between a source diffusion region 102 and a drain diffusion region 108. The “gate length” of transistor 100 is the width of the polysilicon line 104 in the gate region 106 between source diffusion region 102 and drain diffusion region 108. This gate length is indicated by the arrows in FIG. 1.
When this gate length decreases, the off-state leakage current, Ioff, increases as is illustrated in the graph in FIG. 2. Note that as the gate length, L, decreases in FIG. 2, off-state leakage current, Ioff, for the fast transistor increases by almost two orders of magnitude.
FIG. 3 presents a graph of off-state leakage current as a function of drive current in accordance with an embodiment of the invention. As can be seen FIG. 3, as the drive current for the transistor, Ion, increases past 50 μA, there is a corresponding increase in off-state leakage current Ioff. Hence, the increased performance resulting from this additional drive current, Ion, is accompanied by a corresponding increase in off-state current, Ioff, which increases the static power consumption of the chip. This increased static power consumption can be especially troublesome for portable computing devices with limited battery life.
What is needed is a method and an apparatus for manufacturing an integrated circuit that achieves high-performance while substantially minimizing static power consumption caused by off-state leakage current.
Also note that the use of resolution enhancement techniques (RETs) to reduce gate lengths can increase mask cost and increase mask writer time because RETs increase the complexity of the layout. Moreover, RETs can also increase the time required to perform mask inspection.
Hence, what is needed is a method and an apparatus that minimizes the above-described problems of RETs during the process of manufacturing an integrated circuit that still maintains the desired performance characteristics.